Flyback power supplies are comprised of a rectifier and filter for deriving an unregulated direct current voltage from the line or other source of alternating current voltage, a switch for connecting the direct current voltage across a first inductor, a second inductor magnetically coupled to the first, and a diode and a storage capacitor connected in series across the second inductor. Output power is derived by connecting a load in parallel with the output capacitor. When the switch is closed, an increasing current flows in the first inductor and no current flows in the second inductor because of the polarity with which the diode and the second inductor are connected. When, however, the switch is opened, the current supplied from the rectifier to the first inductor goes to zero and the magnetic field created by the current in the first inductor starts to collapse. This induces a voltage of opposite polarity in the second inductor so that the diode now conducts current that charges the output capacitor.
One way to regulate the output voltage is to close the switch at regularly spaced times and to control the intervals during which the switch remains closed. This method is commonly referred to as constant frequency operation with pulse-width modulation control. The switch closure interval is terminated when a ramp signal, VR, that is initiated at switch closure reaches a value that equals the value of an error signal V.sub.E that is proportional to the difference between the actual output voltage and the desired output voltage.
There is, however, an inherent and unavoidable delay of T.sub.1 between the time when the ramp signal VR and error signal V.sub.E reach equality and the time when the switch can be opened. During this time T.sub.1, the current in the first inductor increases so that when the switch is finally opened, the energy stored in the magnetic field of the first inductor and therefore the charge delivered subsequently to the storage capacitor are greater than required to supply the load by some finite amount. Under normal load, the charge thus erroneously added to the storage capacitor causes the feedback amplifier to lower the error voltage V.sub.E. This shortens subsequent switch closure intervals and reduces the transferred charge to the required steady state level. As the load is decreased, the accommodation of the error caused by the delay T.sub.1 can be attained by further reduction of the error voltage V.sub.E until such time that V.sub.E reaches a value of zero. No further reduction of the switch closure interval is then possible and the switch must remain closed for a minimum time of T.sub.1 seconds every time that it is closed. Because a finite amount of charge is transferred upon each switch closure, accurate regulation of the system at no load is not attainable since the average charge required at no load is zero. If the system is required to operate at virtually no load, it must change to a constant pulse width, variable frequency mode of operation, which is often undesirable due to the increased difficulty of filtering the lower frequencies that result.